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Impala Linear Corporation
ILC7080/81
50/100mA SOT-23 CMOS RF LDOTM Regulators
General Description The ILC7080/81 are 50 or 100mA low dropout (LDO) voltage regulators designed to provide a high performance solution to low power systems. The devices offer a typical combination of low dropout and low quiescent current expected of CMOS parts, while uniquely providing the low noise and high ripple rejection characteristics usually only associated with bipolar LDO regulators. The devices have been optimized to meet the needs of modern wireless communications design; Low noise, low dropout, small size, high peak current, high noise immunity. The ILC7080/81 are designed to make use of low cost ceramic capacitors while outperforming other devices that require tantalum capacitors.
Features * Ultra low 1mV dropout per 1mA load * 1% output voltage accuracy * Uses low ESR ceramic output capacitor to minimize noise and output ripple * Only 100A ground current at 100mA load * Ripple rejection up to 85dB at 1kHz, 60dB at 1MHz * Less than 80VRMS noise at BW = 100Hz to 100kHz * Excellent line and load transient response * Over current / over temperature protection * Guaranteed up to 80/150mA output current * Industry standard five lead SOT-23 package * Fixed 2.85V, 3.0V, 3.3V, 3.6V, 4.7V, 5.0V and adjustable output voltage options * Metal mask option available for custom voltages between 2.5 to 10V Applications * * * * Cellular phones Wireless communicators PDAs / palmtops / organizers Battery powered portable electronics
Typical Circuit
VOUT
5
SOT23-5 4 ILC7080 ILC7081
CNOISE
3
COUT VIN
1
Ordering Information (TA = -40C to +85C) ILC7080AIM5-xx 50mA, fixed voltage ILC7080AIM5-ADJ 50mA adjustable voltage ILC7081AIM5-xx 100mA, fixed voltage ILC7081AIM5-ADJ 100mA, adjustable voltage
Note: Fixed voltage options are defined by 2-digit code as shown in the package markings information section of the datasheet.
2
ON OFF
Impala Linear Corporation
ILC7080/81 1.1
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Sept. 1998
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50/100mA SOT-23 CMOS RF LDOTM Regulators
Pin Description ILC7081/81-xx (fixed voltage version)
Pin Number 1 2 3 4 Pin Name VIN GND ON/OFF CNOISE Pin Description Connect direct to supply Ground pin. Local ground for CNOISE and COUT. By applying less than 0.4V to this pin the device will be turned off. Optional noise bypass capacitor may be connected between this pin and GND (pin 2). Do not connect CNOISE directly to the main power ground plane. Output Voltage. Connect COUT between this pin and GND (pin 2)
5
VOUT
Pin Description ILC7081/81-ADJ (adjustable voltage version)
Pin Number 1 2 3 4 5 Pin Name VIN GND ON/OFF VADJ VOUT Pin Description Connect direct to supply Ground pin. Local ground for CNOISE and COUT. By applying less than 0.4V to this pin the device will be turned off. Voltage feedback pin to set the adjustable output voltage. Do not connect a capacitor to this pin. Output Voltage. Connect COUT between this pin and GND (pin 2)
Pin Package Configurations
VOUT
5
CNOISE SOT23-5 4
VOUT
5
VADJ SOT23-5 4
ILC7080-xx ILC7081-xx
1 2 3
ILC7080-ADJ ILC7081-ADJ
1 2 3
VIN
GND
ON OFF
VIN
GND
ON OFF
Impala Linear Corporation
ILC7080/81 1.1
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50/100mA SOT-23 CMOS RF LDOTM Regulators
Absolute Maximum Ratings (Note 1)
Parameter Input voltage On/Off Input voltage Output Current Output voltage Package Power Dissipation (SOT-23-5) Maximum Junction Temp Range Storage Temperature Operating Ambient Temperature Package Thermal Resistance Symbol VIN VON/OFF IOUT VOUT PD TJ(max) TSTG TA JA Ratings -0.3 to +13.5 -0.3 to VIN Short circuit protected -0.3 to VIN+0.3 250 (Internally Limited) -40~+150 -40~+125 -40 to +85 333 Units V mA V mW C C C C/W
Absolute Maximum Ratings (Note 1)
Unless otherwise specified, all limits are at TA = 25C; VIN = VOUT(NOM) + 1V, IOUT = 1mA, COUT = 1F, VON/OFF = 2V. Boldface limits apply over the operating temperature range. (Note 2)
Parameter Input Voltage Range Output voltage
Symbol VIN VOUT
Conditions IOUT = 1mA 1mA < IOUT < 100mA 1mA < IOUT < 100mA
Feedback Voltage (ADJ version) Line Regulation Dropout voltage (Note 3)
VADJ VOUT/ (VOUT*VIN) VOUT(NOM) + 1V < VIN < 12V IOUT = 0mA 7080/81 VIN - VOUT IOUT = 50mA IOUT = 100mA 7081 only IOUT = 150mA IOUT = 10mA
Min 2 -1 -1.5 -3.5 1.215 1.202
Typ VOUT(NOM)
1.240 0.007 0.1 10 50 100 150
Max 13 +1 1.5 +3.5 1.265 1.278 0.014 0.032 1 2 25 35 75 100 150 200 225 300
Units V %
V %/V
mV
Impala Linear Corporation
ILC7080/81 1.1
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50/100mA SOT-23 CMOS RF LDOTM Regulators
Electrical Characteristics ILC7080/81AIM5 (cont.)
Unless otherwise specified, all limits are TA = 25C; VIN = VOUT(NOM) + 1V, IOUT = 1mA, COUT = 1F, VON/OFF = 2V. Boldface limits apply over the operating temperature range. (Note 2)
Parameter
Symbol
Conditions IOUT = 0mA 7080/81 IOUT = 10mA IOUT = 50mA IOUT = 100mA 7081 only IOUT = 150mA
Min
Typ 95 100 100 100 115 0.1
Ground Pin Current
IGND
Shutdown (OFF) Current ON/OFF Input Voltage ON/OFF Pin Input Current (Note 5) Peak Output Current (Note 4) Output Noise Voltage
ION/OFF VON/OFF IIN(ON/OFF) IOUT(PEAK) eN VOUT/VIN VOUT(line)
Ripple Rejection
Dynamic Line Regulation
Dynamic Load Regulation
VOUT(load)
Short Circuit Current
ISC
VON/OFF = 0V High = Regulator On Low = Regulator Off VON/OFF = 0.6V, regulator OFF VON/OFF = 2V, regulator ON VOUT > 0.95VOUT(NOM), tpw = 2ms BW = 300Hz to 50kHz, CNOISE = 0.01F COUT = 4.7F, freq = 1kHz IOUT = 100mA freq = 10kHz freq = 1MHz VIN: VOUT(NOM) + 1V to VOUT(NOM) + 2V, tr/tf = 2s; IOUT = 100mA IOUT: 0 to 100mA; d(IOUT)/dt = 100mA/s with COUT = 0.47F with COUT = 2.2F VOUT = 0V
2.0 0.3 1 500 80 85 70 60 4
Max 200 220 220 240 220 240 240 260 260 280 2 13 0.6
Units
A
A V A mA VRMS
400
dB mV
50 25 600 mV
mA
Note 1: Absolute maximum ratings indicate limits which when exceeded may result in damage to the component. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Note 2: Specified Min/Max limits are production tested or guaranteed through correlation based on statistical control methods. Measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing. Note 3: Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the nominal value measured with a 1V differential. Note 4: Guaranteed by design Note 5: The device's shutdown pin includes a 2MW internal pull down resistor connected to ground.
Impala Linear Corporation
ILC7080/81 1.1
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50/100mA SOT-23 CMOS RF LDOTM Regulators
Operation The ILC7080/81 LDO design is based on an advanced circuit configuration for which patent protection has been applied. Typically it is very difficult to drive a capacitive output with an amplifier. The output capacitance produces a pole in the feedback path, which upsets the carefully tailored dominant pole of the internal amplifier. Traditionally the pole of the output capacitor has been "eliminated" by reducing the output impedance of the regulator such that the pole of the output capacitor is moved well beyond the gain bandwidth product of the regulator. In practice, this is difficult to do and still maintain high frequency operation. Typically the output impedance of the regulator is not simply resistive, such that the reactive output impedance interacts with the reactive impedance of the load resistance and capacitance. In addition, it is necessary to place the dominant pole of the circuit at a sufficiently low frequency such that the gain of the regulator has fallen below unity before any of the complex interactions between the output and the load occur. The ILC7080/81 does not try to eliminate the output pole, but incorporates it into the stability scheme. The load and output capacitor forms a pole, which rolls off the gain of the regulator below unity. In order to do this the output impedance of the regulator must be high, looking like a current source. The output stage of the regulator becomes a transconductance amplifier, which converts a voltage to a current with a substantial output impedance. The circuit which drives the transconductance amplifier is the error amplifier, which compares the regulator output to the band gap reference and produces an error voltage as the input to the transconductance amplifier. The error amplifier has a dominant pole at low frequency and a "zero" which cancels out the effects of the pole. The zero allows the regulator to have gain out to the frequency where the output pole continues to reduce the gain to unity. The configuration of the poles and zero are shown in figure 1. Instead of powering the critical circuits from the unregulated input voltage, the CMOS RF LDO powers the internal circuits such as the bandgap, the error amplifier and most of the transconductance amplifier from the boot strapped regulated output voltage of the regulator. This technique offers extremely high ripple rejection and excellent line transient response. A block diagram of the regulator circuit used in the ILC7080/81 is shown in figure 2, which shows the input-tooutput isolation and the cascaded sequence of amplifiers that implement the pole-zero scheme outlined above. The ILC7080/81 were designed in a CMOS process with some minor additions, which allow the circuit to be used at input voltages up to 13V. The resulting circuit exceeds the frequency response of traditional bipolar circuits. The ILC7080/81 is very tolerant of output load conditions with the inclusion of both short circuit and thermal overload protection. The device has a very low dropout voltage, typically a linear response of 1mV per milliamp of load current, and none of the quasi-saturation characteristics of a bipolar output device. All the good features of the frequency response and regulation are valid right to the point where the regulator goes out of regulation in a 4mV transition region. Because there is no base drive, the regulator is capable of providing high current surges while remaining in regulation. This is shown in the high peak current of 500mA which allows for the ILC7080/81 to be used in systems that require short burst mode operation.
DOMINANT POLE 85 dB
GAIN
OUTPUT POLE
COMPENSATING ZERO
UNITY GAIN
FREQUENCY
Figure 1: ILC7080/81 RF LDO frequency response
Impala Linear Corporation
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50/100mA SOT-23 CMOS RF LDOTM Regulators
INTERNAL VDD
VIN CNOISE
BANDGAP REFERENCE VREF ERROR AMPLIFIER TRANSCONDUCTANCE AMPLIFIER
VOUT
FEEDBACK
GND
ON/OFF
Figure 2: ILC7080/81 RF LDO regulator block digram Shutdown (ON/OFF) Operation The ILC7080/81 output can be turned off by applying 0.4V or less to the device's ON/OFF pin (pin 3). In shutdown mode, the ILC7080/81 draws less than 1mA quiescent current. The output of the ILC7081 is enabled by applying 2V to 13V at the ON/OFF pin. In applications where the ILC7080/81 output will always remain enabled, the ON/OFF pin may be connected to VIN (pin 1). The ILC7080/81's shutdown circuitry includes hysteresis, as such the device will operate properly even if a slow moving signal is applied to the ON/OFF pin. The device's shutdown pin includes a 2M internal pull down resistor connected to ground. Short Circuit Protection The ILC7080/81 output can withstand momentary short circuit to ground. Moreover, the regulator can deliver very high output peak current due to its 1A instantaneous short circuit current capability. Thermal Protection The ILC7080/81 also includes a thermal protection circuit which shuts down the regulator when die temperature exceeds 170C due to overheating. In thermal shutdown, once the die temperature cools to below 160C, the regulator is enabled. If the die temperature is excessive due to high package power dissipation, the regulator's thermal circuit will continue to pulse the regulator on and off. This is called thermal cycling. Excessively high die temperature may occur due to high differential voltage across the regulator or high load current or high ambient temperature or a combination of all three. Thermal protection protects the regulator from such fault conditions and is a necessary requirement in today's designs. In normal operation, the die temperature should be limited to under 150C.
Impala Linear Corporation
ILC7080/81 1.1
Adjustable Output Voltage Figure 3 shows how an adjustable output voltage can be easily achieved using ILC7080/81-ADJ. The output voltage, VOUT is given by the following equation: VOUT = 1.24V x (R1/R2 + 1)
R1 VOUT
5
R2
SOT23-5 4 VADJ
COUT VIN CIN
ILC7080-ADJ ILC7081-ADJ
1 2 3
ON OFF
Figure 3: Application circuit for adjustable output voltage
For best results, a resistor value of 470k or less may be used for R2. The output voltage can be programmed from 2.5V to 12V.
Note: An external capacitor should not be connected to the adjustable feedback pin (pin 4). Connecting an external capacitor to pin 4 may cause regulator instability and lead to oscillations.
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50/100mA SOT-23 CMOS RF LDOTM Regulators
Maximum Output Current The maximum output current available from the ILC7080/81 is limited by the maximum package power dissipation as well as the device's internal current limit. For a given ambient temperature, TA, the maximum package power dissipation is given by: PD(max) = (TJ(max) - TA) / JA where TJ(max) = 150C is the maximum junction temperature and JA = 333C/W is the package thermal resistance. For example at TA = 85C ambient temperature, the maximum package power dissipation is; PD(max) = 195mW. The maximum output current can be calculated from the following equation: IOUT(max) < PD(max) / (VIN - VOUT) For example at VIN = 6V, VOUT = 5V and TA = 85C, the maximum output current is IOUT(max) < 195mA. At higher output current, the die temperature will rise and cause the thermal protection circuit to be enabled. APPLICATION HINTS Figure 4 shows the typical application circuit for the ILC7080/81.
VOUT
5
CIN, will hold VIN higher than VOUT and decay slower than VOUT when the LDO is powered off. Output Capacitor Selection Impala strongly recommends the use of low ESR (equivalent series resistance) ceramic capacitors for COUT and CNOISE. The ILC7080/81 is stable with low ESR capacitor (as low as zero ). The value of the output capacitor should be 1F or higher. Either ceramic chip or a tantalum capacitor may be used at the output. Use of ceramic chip capacitors offer significant advantages over tantalum capacitors. A ceramic capacitor is typically considerably cheaper than a tantalum capacitor, it usually has a smaller footprint, lower height, and lighter weight than a tantalum capacitor. Furthermore, unlike tantalum capacitors which are polarized and can be damaged if connected incorrectly, ceramic capacitors are non-polarized. Low value ceramic chip capacitors with X7R dielectric are available in the 100pF to 4.7F range, while high value capacitors with Y5V dielectric are available in the 2200pF to 22F range. Evaluate carefully before using capacitors with Y5V dielectric because their ESR increases significantly at cold temperatures. Figure 10 shows a list of recommended ceramic capacitors for use at the output of ILC7080/81.
Note: If a tantalum output capacitor is used then for stable operation Impala recommends a low ESR tantalum capacitor with maximum rated ESR at or below 0.4. Low ESR tantalum capacitors, such as the TPS series from AVX Corporation (www.avxcorp.com) or the T495 series from Kemet (www.kemet.com) may be used.
SOT23-5 4 ILC7080 ILC7081
CNOISE
3
COUT VIN
1
2
In applications where a high output surge current can be expected, use a high value but low ESR output capacitor for superior load transient response. The ILC7080/81 is stable with no load. Noise Bypass Capacitor In low noise applications, the self noise of the ILC7080/81 can be decreased further by connecting a capacitor from the noise bypass pin (pin 4) to ground (pin 2). The noise bypass pin is a high impedance node as such, care should be taken in printed circuit board layout to avoid noise pickup from external sources. Moreover, the noise bypass capacitor should have low leakage. Noise bypass capacitors with a value as low as 470pF may be used. However, for optimum performance, use a 0.01F or larger, ceramic chip capacitor. Note that the turn on and turn off response of the ILC7080/81 is inversely proportional to the value of the noise bypass capacitor. For fast turn on and turn off, use a small value noise bypass capacitor. In applications were exceptionally low output noise is not required, consider omitting the noise bypass capacitor altogether.
ON OFF
Figure 4: Basic application circuit for fixed output voltage versions
Input Capacitor An input capacitor CIN of value 1mF or larger should be connected from VIN to the main ground plane. This will help to filter supply noise from entering the LDO. The input capacitor should be connected as close to the LDO regulator input pin as is practical. Using a high-value input capacitor will offer superior line transient response as well as better power supply ripple rejection. A ceramic or tantalum capacitor may be used at the input of the LDO regulator. Note that there is a parasitic diode from the LDO regulator output to the input. If the input voltage swings below the regulator's output voltage by a couple of hundred milivolts then the regulator may be damaged. This condition must be avoided. In many applications a large value input capacitor,
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50/100mA SOT-23 CMOS RF LDOTM Regulators
The Effects of ESR (Equivalent Series Resistance) The ESR of a capacitor is a measure of the resistance due to the leads and the internal connections of the component. Typically measured in m (milli-ohms) it can increase to ohms in some cases. Wherever there is a combination of resistance and current, voltages will be present. The control functions of LDOs use two voltages in order to maintain the output precisely; VOUT and VREF. With reference to the block diagram in figure 2, VOUT is fed back to the error amplifier and is used as the supply voltage for the internal components of the 7080/81. So any change in VOUT will cause the error amplifier to try to compensate to maintain VOUT at the set level and noise on VOUT will be reflected into the supply of each internal circuit. The reference voltage, VREF, is influenced by the CNOISE pin. Noise into this pin will add to the reference voltage and be fed through the circuit. These factors will not cause a problem if some simple steps are taken. Figure 5 shows where these added ESR resistances are present in the typical LDO circuit.
VOUT
IC
Printed Circuit Board Layout Guidelines As was mentioned in the previous section, to take full advantage of any high performance LDO regulator requires paying careful attention to grounding and printed circuit board (PCB) layout.
VOUT
RPCB
IOUT
ESR
I2
5
RPCB
RPCB
ESR CNOISE
I1
COUT
SOT23-5 4
ILC7080 ILC7081
1 2
RPCB
VIN VIN
RPCB
3
ON OFF
Figure 6: Inherent PCB resistance
Figure 7 shows the effects of poor grounding and PCB layout caused by the ESR and PCB resistances and the accumulation of current flows. Note particularly that during high output load current, the LDO regulator's ground pin and the ground return for COUT and CNOISE are not at the same potential as the system ground. This is due to high frequency impedance caused by PCB's trace inductance and DC resistance. The current loop between COUT, CNOISE and the LDO regulator's ground pin will degrade performance of the LDO.
IOUT
RC 5
SOT23-5 4
R* CNOISE
COUT VIN R* CIN
1
ILC7080 ILC7081
2 RF LDOTM Regulator 3
ON OFF
5 4
Figure 5: ESR in COUT and CNOISE
With this in mind low ESR components will offer better performance as LDOs may be exposed to large transients of output voltage, and current flows through the capacitors in order to filter these transient swings. ESR is less of a problem with CIN as the voltage fluctuations at the input will be filtered by the LDO. However, being aware of these current flows, there is also another potential source of induced voltage noise from the resistance inherent in the PCB trace. Figure 6 shows where the additive resistance of the PCB can manifest itself. Again these resistances may be very small, but a summation of several currents can develop detectable voltage ripple and will be amplified by the LDO. Particularly the accumulation of current flows in the ground plane can develop significant voltages unless care is taken. With a degree of care, the ILC7080/81 will yield outstanding performance.
1
2
3
Figure 7: Effects of poor circuit layout
Figure 8 shows an optimum schematic. In this schematic, high output surge current has little effect on the ground current and noise bypass current return of the LDO regulator. Note that the key difference here is that COUT and CNOISE are directly connected to the LDO regulator's ground pin. The LDO is then separately connected to the main ground plane and returned to a single point system ground. The layout of the LDO and its external components are also based on some simple rules to minimize EMI and output voltage ripple.
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LOAD
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50/100mA SOT-23 CMOS RF LDOTM Regulators
5
4
1
2
3
Figure 8: Recommended application circuit schematic
Figure 9: Recommended application circuit layout (not drawn to scale). Note: ground plane is bottom layer of PCB and connects to top layer ground connections through vias
Evaluation Board Parts List For Printed Circuit Board Shown Above
Label U1 J1 CIN CNOISE COUT Part Number ILC7081AIM5-30 69190-405 GRM40 Y5V 105Z16 ECU-V1H103KBV GRM426X5R475K10 Manufacturer Impala Linear Berg muRata Panasonic muRata Description 100mA RF LDOTM Connector, four position header Ceramic capacitor, 1F, 16V, SMT (size 0805) Ceramic Capacitor, 0.01F, 16V, SMT (size 0603) Ceramic Capacitor, 4.7F, 16V, SMT (size 1206)
Grounding Recommendations 1. Connect CIN between VIN of the ILC7080/81 and the "GROUND PLANE". 2. Keep the ground side of COUT and CNOISE connected to the "LOCAL GROUND" and not directly to the "GROUND PLANE". 3. On multilayer boards use component side copper for grounding around the ILC7080/81 and connect back to a "GROUND PLANE" using vias. 4. If using a DC-DC converter in your design, use a star grounding system with separate traces for the power ground and the control signals. The star should radiate from where the power supply enters the PCB.
Layout Considerations 1. Place all RF LDO related components; ILC7080/81, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT as close together as possible. 2. Keep the output capacitor COUT as close to the ILC7080/81 as possible with very short traces to the VOUT and GND pins. 3. The traces for the related components; ILC7080/81, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT can be run with minimum trace widths close to the LDO. 4. Maintain a separate "LOCAL GROUND" remote from the "GROUND PLANE" to ensure a quiet ground near the LDO. Figure 9 shows how this circuit can be translated into a PCB layout.
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50/100mA SOT-23 CMOS RF LDOTM Regulators
Recommended Ceramic Output Capacitors
COUT 1F 1F 1F 1F 1F 1F 2.2F 2.2F 2.2F 4.7F 4.7F Capacitor Size 0805 0805 0805 1206 1206 1206 0805 0805 1206 1206 1206 IOUT 0 to 100mA 0 to 100mA 0 to 100mA 0 to 100mA 0 to 100mA 0 to 100mA 0 to 150mA 0 to 150mA 0 to 150mA 0 to 150mA 0 to 150mA Dielectric X5R X7R X7R X7R X7R X5R X5R X5R X5R X5R X7R Part Number C2012X5R1A105KT GRM40X7R105K010 LMK212BJ105KG GRM42-6X7R105K016 EMK316BJ105KL TMK316BJ105KL GRM40X5R225K 6.3 C2012X5R0J225KT EMK316BJ225ML GRM42-6X5R475K010 LMK316BJ475ML Capacitor Vendor TDK muRata Talyo-Yuden muRata Talyo-Yuden Talyo-Yuden muRata TDK Talyo-Yuden muRata Talyo-Yuden
Impala Linear Corporation
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50/100mA SOT-23 CMOS RF LDOTM Regulators
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified TA T=25C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN Characterization at output currents above 50mA applies to ILC7081
Output Voltage vs Temperature
3.015 3.01
Dropout Characteristics Dropout Characteristics
3.4
V OUT = 3.0V CO UT = 0.47F (Ceramic) 1F (Ceramic)
VO UT = 3.3V 0.47F (Ceramic) COUT = 1F (Ceramic) IOUT = 0mA IOUT = 10mA IOUT = 50mA
Output voltage (V)
3.3 3.005 3 2.995 3.1 2.99 2.985 -50 0 50 100 150 3 3
VOU T (V)
3.2
7081 only
IOUT = 100mA IOUT = 150mA
3.2
3.4
3.6
Temperature (C)
VIN (V)
Dropout Voltage vs Temperature
250 250
Dropout Voltage vs I OU T VOU T = 3.0V Dropout voltage (mV)
200
VOU T = 3.0V Dropout voltage (mV)
200
IO UT = 150mA
TA = 85C TA = 25C
150
IO UT = 100mA
150
100
100
IOUT = 50mA
50
TA = -40C
50
IOUT = 0mA
0 -40 25 85
0 0 50 100 150
Temperature (C)
Output Current (mA)
Ground Current vs Input Voltage
150
Line Transient Response Line Transient Response
6
VIN (V)
V OUT = 3.0 V IOUT = 10mA 0.47F (Ceramic) COUT = 1F (Ceramic) IOU T = 50mA 125 IOU T = 150mA I GN D (A) IOUT = 0mA
100
5
VIN: tr/tf < 1 s VO UT = 3.0V COUT = 2.2 F (Ceramic) IO UT = 100 mA
4
75
IOUT = 100mA
V OUT (V)
12 14
3.01 3.00 2.99 2.98
50 2 4 6 8 10
VIN (V)
5s/div
Impala Linear Corporation
ILC7080/81 1.1
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50/100mA SOT-23 CMOS RF LDOTM Regulators
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified TA T=25C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN Characterization at output currents above 50mA applies to ILC7081
5s/div
Impala Linear Corporation
ILC7080/81 1.1
(408) 574-3939
www.impalalinear.com
Sept. 1998
12
50/100mA SOT-23 CMOS RF LDOTM Regulators
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified TA T=25C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN Characterization at output currents above 50mA applies to ILC7081
Impala Linear Corporation
ILC7080/81 1.1
(408) 574-3939
www.impalalinear.com
Sept. 1998
13
50/100mA SOT-23 CMOS RF LDOTM Regulators
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified TA T=25C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN Characterization at output currents above 50mA applies to ILC7081
Impala Linear Corporation
ILC7080/81 1.1
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Sept. 1998
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50/100mA SOT-23 CMOS RF LDOTM Regulators
SOT-23 Package Markings
ILC7080AIM5-xx
Output voltage (V) 2.85 3.0 3.3 3.6 5.0 ADJ Grade A A A A A A Order Information ILC7080AIM5-285 ILC7080AIM5-30 ILC7080AIM5-33 ILC7080AIM5-36 ILC7080AIM5-50 ILC7080AIM5-ADJ *Package Marking CFXX CAXX CBXX CDXX CCXX CEXX Supplied as: 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel
*Note: First two characters identify the product and the last two characters identify the date code.
ILC7081AIM5-xx
Output voltage (V) 2.85 3.0 3.3 3.6 4.7 5.0 ADJ Grade A A A A A A A Order Information ILC7081AIM5-285 ILC7081AIM5-30 ILC7081AIM5-33 ILC7081AIM5-36 ILC7081AIM5-47 ILC7081AIM5-50 ILC7081AIM5-ADJ *Package Marking CVXX CQXX CRXX CTXX CWXX CSXX CUXX Supplied as: 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel 3k Units on Tape and Reel
*Note: First two characters identify the product and the last two characters identify the date code.
Impala Linear Corporation
ILC7080/81 1.1
(408) 574-3939
www.impalalinear.com
Sept. 1998
15
50/100mA SOT-23 CMOS RF LDOTM Regulators
Package Outline Dimensions
Dimensions shown in inches and (mm). 5-Lead plastic surface mount (SOT-23-5)
Devices sold by Impala Linear Corporation are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Impala Linear Corporation makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Impala Linear Corporation makes no warranty of merchantability or fitness for any purpose. Impala Linear Corporation reserves the right to discontinue production and change specifications and prices at any time and without notice. This product is intended for use in normal commercial applications. Applications requiring an extended temperature range, unusual environmental requirements, or high reliability applications, such as military and aerospace, are specifically not recommended without additional processing by Impala Linear Corporation. Impala Linear Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Impala Linear Corporation product. No other circuits, patents, licenses are implied.
Life Support Policy Impala Linear Corporation's products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Impala Linear Corporation
ILC7080/81 1.1
(408) 574-3939
www.impalalinear.com
Sept. 1998
16

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